As a non-volatile semiconductor storage device that is electrically writable and erasable, an electrically erasable and programmable read only memory (EEPROM) is widely used. Such storage device represented by a flash memory, which is widely used nowadays, has a conductive floating gate electrode surrounded by an oxide film or a trap insulating film below a gate electrode of a MISFET. A charge storage state of a floating gate or the trap insulating film is used as storage information and is read out as a threshold value of the transistor. The trap insulating film is an insulating film capable of storing a charge, and by way of example, a silicon nitride film is used as such insulating film. By injecting and releasing the charge to such charge storage region, the threshold value of the MISFET is shifted, whereby the MISFET is operated as a storage element. As the flash memory, there is a split gate type cell using a metal-oxide-nitride-oxide-semiconductor (MONOS) film.
As a field effect transistor that has a high operating speed and is capable of reducing a leakage current and power consumption as well as being miniaturized, a fin-type transistor has been known. The fin-type transistor, or a fin field effect transistor (FINFET) is a semiconductor element, for example, having a semiconductor layer pattern formed on a substrate as a channel layer and having a gate electrode formed so as to stride over the pattern.
As a semiconductor device capable of suppressing short channel characteristics and suppressing element variation, a semiconductor device using a silicon-on-insulator (SOI) substrate is currently used. The SOI substrate is a substrate having a supporting substrate composed of highly-resistive silicon (Si) and the like, a buried oxide (BOX) film formed over the supporting substrate, and a thin layer mainly containing Si (silicon layer, SOI layer) formed over the BOX film.
In Japanese Patent Application Laid-Open Publication No. 2005-332502 (Patent Document 1), a memory array (memory cell array) structure of an EEPROM is described.
In Japanese Patent Application Laid-Open Publication No. 2006-041354 (Patent Document 2), a memory array structure of a MONOS memory having a split gate structure is described.